
module frv_idu_rat (
    input                       clk             , 
    input                       rst_n           , 
    input                       pd_rst          , 
    // Regfile Operation
    input [4:0]                 rat_rs1_ind     , 
    input [4:0]                 rat_rs2_ind     , 
    input                       rat_rd_vld      , 
    input [4:0]                 rat_rd_ind      , 
    input [5:0]     rat_rob_wprt    , 
    input                       isq_entry_wen   ,
    // Retire Operation
    input                       ret_rd_req      ,
    input [5:0]     ret_inst_id     , // ROB Read Pointer Val     
    input                       ret_flush_rles  , 
    //FUs Foward
    input                       lsu_fwd_vld     ,
    input                       lsu_fwd_rd_vld  ,
    input [5:0]     lsu_fwd_inst_id ,
    input                       bru_fwd_vld     ,
    input                       bru_fwd_rd_vld  ,
    input [5:0]     bru_fwd_inst_id ,
    // input                       bru_flush       ,
    input                       alu_fwd_vld     ,
    input                       alu_fwd_rd_vld  ,
    input [5:0]     alu_fwd_inst_id ,
    // Reg Map Result
    output[5:0]     rat_rs1_map     ,
    output                      rat_rs1_type    , // ARCH: 0 ,ROB: 1
    output                      rat_rs1_ready   ,
    output[5:0]     rat_rs2_map     ,
    output                      rat_rs2_type    , // ARCH: 0 ,ROB: 1
    output                      rat_rs2_ready   
    // output[5:0]     rat_inst_id_o           
);

wire[5:0]    rat_rs1_map_nxt;
wire                     rat_rs1_type_nxt;
wire                     rat_rs1_ready_nxt;
wire[5:0]    rat_rs2_map_nxt;
wire                     rat_rs2_type_nxt;
wire                     rat_rs2_ready_nxt;

//RAT Entries
wire                     entry_ready_0,entry_ready_nxt_0;
wire                     entry_type_0,entry_type_nxt_0;
wire [5:0]   entry_id_0,entry_id_nxt_0;
wire                     entry_ready_wen_0;
wire                     entry_type_wen_0;
wire                     entry_id_wen_0;
wire                     entry_req_wen_0;
wire                     entry_ready_1,entry_ready_nxt_1;
wire                     entry_type_1,entry_type_nxt_1;
wire [5:0]   entry_id_1,entry_id_nxt_1;
wire                     entry_ready_wen_1;
wire                     entry_type_wen_1;
wire                     entry_id_wen_1;
wire                     entry_req_wen_1;
wire                     entry_ready_2,entry_ready_nxt_2;
wire                     entry_type_2,entry_type_nxt_2;
wire [5:0]   entry_id_2,entry_id_nxt_2;
wire                     entry_ready_wen_2;
wire                     entry_type_wen_2;
wire                     entry_id_wen_2;
wire                     entry_req_wen_2;
wire                     entry_ready_3,entry_ready_nxt_3;
wire                     entry_type_3,entry_type_nxt_3;
wire [5:0]   entry_id_3,entry_id_nxt_3;
wire                     entry_ready_wen_3;
wire                     entry_type_wen_3;
wire                     entry_id_wen_3;
wire                     entry_req_wen_3;
wire                     entry_ready_4,entry_ready_nxt_4;
wire                     entry_type_4,entry_type_nxt_4;
wire [5:0]   entry_id_4,entry_id_nxt_4;
wire                     entry_ready_wen_4;
wire                     entry_type_wen_4;
wire                     entry_id_wen_4;
wire                     entry_req_wen_4;
wire                     entry_ready_5,entry_ready_nxt_5;
wire                     entry_type_5,entry_type_nxt_5;
wire [5:0]   entry_id_5,entry_id_nxt_5;
wire                     entry_ready_wen_5;
wire                     entry_type_wen_5;
wire                     entry_id_wen_5;
wire                     entry_req_wen_5;
wire                     entry_ready_6,entry_ready_nxt_6;
wire                     entry_type_6,entry_type_nxt_6;
wire [5:0]   entry_id_6,entry_id_nxt_6;
wire                     entry_ready_wen_6;
wire                     entry_type_wen_6;
wire                     entry_id_wen_6;
wire                     entry_req_wen_6;
wire                     entry_ready_7,entry_ready_nxt_7;
wire                     entry_type_7,entry_type_nxt_7;
wire [5:0]   entry_id_7,entry_id_nxt_7;
wire                     entry_ready_wen_7;
wire                     entry_type_wen_7;
wire                     entry_id_wen_7;
wire                     entry_req_wen_7;
wire                     entry_ready_8,entry_ready_nxt_8;
wire                     entry_type_8,entry_type_nxt_8;
wire [5:0]   entry_id_8,entry_id_nxt_8;
wire                     entry_ready_wen_8;
wire                     entry_type_wen_8;
wire                     entry_id_wen_8;
wire                     entry_req_wen_8;
wire                     entry_ready_9,entry_ready_nxt_9;
wire                     entry_type_9,entry_type_nxt_9;
wire [5:0]   entry_id_9,entry_id_nxt_9;
wire                     entry_ready_wen_9;
wire                     entry_type_wen_9;
wire                     entry_id_wen_9;
wire                     entry_req_wen_9;
wire                     entry_ready_10,entry_ready_nxt_10;
wire                     entry_type_10,entry_type_nxt_10;
wire [5:0]   entry_id_10,entry_id_nxt_10;
wire                     entry_ready_wen_10;
wire                     entry_type_wen_10;
wire                     entry_id_wen_10;
wire                     entry_req_wen_10;
wire                     entry_ready_11,entry_ready_nxt_11;
wire                     entry_type_11,entry_type_nxt_11;
wire [5:0]   entry_id_11,entry_id_nxt_11;
wire                     entry_ready_wen_11;
wire                     entry_type_wen_11;
wire                     entry_id_wen_11;
wire                     entry_req_wen_11;
wire                     entry_ready_12,entry_ready_nxt_12;
wire                     entry_type_12,entry_type_nxt_12;
wire [5:0]   entry_id_12,entry_id_nxt_12;
wire                     entry_ready_wen_12;
wire                     entry_type_wen_12;
wire                     entry_id_wen_12;
wire                     entry_req_wen_12;
wire                     entry_ready_13,entry_ready_nxt_13;
wire                     entry_type_13,entry_type_nxt_13;
wire [5:0]   entry_id_13,entry_id_nxt_13;
wire                     entry_ready_wen_13;
wire                     entry_type_wen_13;
wire                     entry_id_wen_13;
wire                     entry_req_wen_13;
wire                     entry_ready_14,entry_ready_nxt_14;
wire                     entry_type_14,entry_type_nxt_14;
wire [5:0]   entry_id_14,entry_id_nxt_14;
wire                     entry_ready_wen_14;
wire                     entry_type_wen_14;
wire                     entry_id_wen_14;
wire                     entry_req_wen_14;
wire                     entry_ready_15,entry_ready_nxt_15;
wire                     entry_type_15,entry_type_nxt_15;
wire [5:0]   entry_id_15,entry_id_nxt_15;
wire                     entry_ready_wen_15;
wire                     entry_type_wen_15;
wire                     entry_id_wen_15;
wire                     entry_req_wen_15;
wire                     entry_ready_16,entry_ready_nxt_16;
wire                     entry_type_16,entry_type_nxt_16;
wire [5:0]   entry_id_16,entry_id_nxt_16;
wire                     entry_ready_wen_16;
wire                     entry_type_wen_16;
wire                     entry_id_wen_16;
wire                     entry_req_wen_16;
wire                     entry_ready_17,entry_ready_nxt_17;
wire                     entry_type_17,entry_type_nxt_17;
wire [5:0]   entry_id_17,entry_id_nxt_17;
wire                     entry_ready_wen_17;
wire                     entry_type_wen_17;
wire                     entry_id_wen_17;
wire                     entry_req_wen_17;
wire                     entry_ready_18,entry_ready_nxt_18;
wire                     entry_type_18,entry_type_nxt_18;
wire [5:0]   entry_id_18,entry_id_nxt_18;
wire                     entry_ready_wen_18;
wire                     entry_type_wen_18;
wire                     entry_id_wen_18;
wire                     entry_req_wen_18;
wire                     entry_ready_19,entry_ready_nxt_19;
wire                     entry_type_19,entry_type_nxt_19;
wire [5:0]   entry_id_19,entry_id_nxt_19;
wire                     entry_ready_wen_19;
wire                     entry_type_wen_19;
wire                     entry_id_wen_19;
wire                     entry_req_wen_19;
wire                     entry_ready_20,entry_ready_nxt_20;
wire                     entry_type_20,entry_type_nxt_20;
wire [5:0]   entry_id_20,entry_id_nxt_20;
wire                     entry_ready_wen_20;
wire                     entry_type_wen_20;
wire                     entry_id_wen_20;
wire                     entry_req_wen_20;
wire                     entry_ready_21,entry_ready_nxt_21;
wire                     entry_type_21,entry_type_nxt_21;
wire [5:0]   entry_id_21,entry_id_nxt_21;
wire                     entry_ready_wen_21;
wire                     entry_type_wen_21;
wire                     entry_id_wen_21;
wire                     entry_req_wen_21;
wire                     entry_ready_22,entry_ready_nxt_22;
wire                     entry_type_22,entry_type_nxt_22;
wire [5:0]   entry_id_22,entry_id_nxt_22;
wire                     entry_ready_wen_22;
wire                     entry_type_wen_22;
wire                     entry_id_wen_22;
wire                     entry_req_wen_22;
wire                     entry_ready_23,entry_ready_nxt_23;
wire                     entry_type_23,entry_type_nxt_23;
wire [5:0]   entry_id_23,entry_id_nxt_23;
wire                     entry_ready_wen_23;
wire                     entry_type_wen_23;
wire                     entry_id_wen_23;
wire                     entry_req_wen_23;
wire                     entry_ready_24,entry_ready_nxt_24;
wire                     entry_type_24,entry_type_nxt_24;
wire [5:0]   entry_id_24,entry_id_nxt_24;
wire                     entry_ready_wen_24;
wire                     entry_type_wen_24;
wire                     entry_id_wen_24;
wire                     entry_req_wen_24;
wire                     entry_ready_25,entry_ready_nxt_25;
wire                     entry_type_25,entry_type_nxt_25;
wire [5:0]   entry_id_25,entry_id_nxt_25;
wire                     entry_ready_wen_25;
wire                     entry_type_wen_25;
wire                     entry_id_wen_25;
wire                     entry_req_wen_25;
wire                     entry_ready_26,entry_ready_nxt_26;
wire                     entry_type_26,entry_type_nxt_26;
wire [5:0]   entry_id_26,entry_id_nxt_26;
wire                     entry_ready_wen_26;
wire                     entry_type_wen_26;
wire                     entry_id_wen_26;
wire                     entry_req_wen_26;
wire                     entry_ready_27,entry_ready_nxt_27;
wire                     entry_type_27,entry_type_nxt_27;
wire [5:0]   entry_id_27,entry_id_nxt_27;
wire                     entry_ready_wen_27;
wire                     entry_type_wen_27;
wire                     entry_id_wen_27;
wire                     entry_req_wen_27;
wire                     entry_ready_28,entry_ready_nxt_28;
wire                     entry_type_28,entry_type_nxt_28;
wire [5:0]   entry_id_28,entry_id_nxt_28;
wire                     entry_ready_wen_28;
wire                     entry_type_wen_28;
wire                     entry_id_wen_28;
wire                     entry_req_wen_28;
wire                     entry_ready_29,entry_ready_nxt_29;
wire                     entry_type_29,entry_type_nxt_29;
wire [5:0]   entry_id_29,entry_id_nxt_29;
wire                     entry_ready_wen_29;
wire                     entry_type_wen_29;
wire                     entry_id_wen_29;
wire                     entry_req_wen_29;
wire                     entry_ready_30,entry_ready_nxt_30;
wire                     entry_type_30,entry_type_nxt_30;
wire [5:0]   entry_id_30,entry_id_nxt_30;
wire                     entry_ready_wen_30;
wire                     entry_type_wen_30;
wire                     entry_id_wen_30;
wire                     entry_req_wen_30;
wire                     entry_ready_31,entry_ready_nxt_31;
wire                     entry_type_31,entry_type_nxt_31;
wire [5:0]   entry_id_31,entry_id_nxt_31;
wire                     entry_ready_wen_31;
wire                     entry_type_wen_31;
wire                     entry_id_wen_31;
wire                     entry_req_wen_31;

wire[5:0]   rs1_index_map;
wire[5:0]   rs2_index_map;
wire                    rs1_rat_ready; // Table Select
wire                    rs2_rat_ready;
wire                    rs1_rat_type ; 
wire                    rs2_rat_type ;
// If Type==0 ,it's Ready ,If Type==1 , it depends on rs1_rat_ready
wire                    rs1_ready;
wire                    rs2_ready;
wire                    rs1_type;
wire                    rs2_type;

wire                    rs1_retire_match;
wire                    rs2_retire_match;

wire                    rs1_fu_match; //RS1 Function Unit Match
wire                    rs2_fu_match;

// Get Register Map
assign rs1_rat_ready = rat_rs1_ind == 0 | 
         ({rat_rs1_ind == 1} && entry_ready_1) |
         ({rat_rs1_ind == 2} && entry_ready_2) |
         ({rat_rs1_ind == 3} && entry_ready_3) |
         ({rat_rs1_ind == 4} && entry_ready_4) |
         ({rat_rs1_ind == 5} && entry_ready_5) |
         ({rat_rs1_ind == 6} && entry_ready_6) |
         ({rat_rs1_ind == 7} && entry_ready_7) |
         ({rat_rs1_ind == 8} && entry_ready_8) |
         ({rat_rs1_ind == 9} && entry_ready_9) |
         ({rat_rs1_ind == 10} && entry_ready_10) |
         ({rat_rs1_ind == 11} && entry_ready_11) |
         ({rat_rs1_ind == 12} && entry_ready_12) |
         ({rat_rs1_ind == 13} && entry_ready_13) |
         ({rat_rs1_ind == 14} && entry_ready_14) |
         ({rat_rs1_ind == 15} && entry_ready_15) |
         ({rat_rs1_ind == 16} && entry_ready_16) |
         ({rat_rs1_ind == 17} && entry_ready_17) |
         ({rat_rs1_ind == 18} && entry_ready_18) |
         ({rat_rs1_ind == 19} && entry_ready_19) |
         ({rat_rs1_ind == 20} && entry_ready_20) |
         ({rat_rs1_ind == 21} && entry_ready_21) |
         ({rat_rs1_ind == 22} && entry_ready_22) |
         ({rat_rs1_ind == 23} && entry_ready_23) |
         ({rat_rs1_ind == 24} && entry_ready_24) |
         ({rat_rs1_ind == 25} && entry_ready_25) |
         ({rat_rs1_ind == 26} && entry_ready_26) |
         ({rat_rs1_ind == 27} && entry_ready_27) |
         ({rat_rs1_ind == 28} && entry_ready_28) |
         ({rat_rs1_ind == 29} && entry_ready_29) |
         ({rat_rs1_ind == 30} && entry_ready_30) |
         ({rat_rs1_ind == 31} && entry_ready_31) ;


assign rs1_rat_type = 
         ({rat_rs1_ind == 1} && entry_type_1)  |
         ({rat_rs1_ind == 2} && entry_type_2)  |
         ({rat_rs1_ind == 3} && entry_type_3)  |
         ({rat_rs1_ind == 4} && entry_type_4)  |
         ({rat_rs1_ind == 5} && entry_type_5)  |
         ({rat_rs1_ind == 6} && entry_type_6)  |
         ({rat_rs1_ind == 7} && entry_type_7)  |
         ({rat_rs1_ind == 8} && entry_type_8)  |
         ({rat_rs1_ind == 9} && entry_type_9)  |
         ({rat_rs1_ind == 10} && entry_type_10)  |
         ({rat_rs1_ind == 11} && entry_type_11)  |
         ({rat_rs1_ind == 12} && entry_type_12)  |
         ({rat_rs1_ind == 13} && entry_type_13)  |
         ({rat_rs1_ind == 14} && entry_type_14)  |
         ({rat_rs1_ind == 15} && entry_type_15)  |
         ({rat_rs1_ind == 16} && entry_type_16)  |
         ({rat_rs1_ind == 17} && entry_type_17)  |
         ({rat_rs1_ind == 18} && entry_type_18)  |
         ({rat_rs1_ind == 19} && entry_type_19)  |
         ({rat_rs1_ind == 20} && entry_type_20)  |
         ({rat_rs1_ind == 21} && entry_type_21)  |
         ({rat_rs1_ind == 22} && entry_type_22)  |
         ({rat_rs1_ind == 23} && entry_type_23)  |
         ({rat_rs1_ind == 24} && entry_type_24)  |
         ({rat_rs1_ind == 25} && entry_type_25)  |
         ({rat_rs1_ind == 26} && entry_type_26)  |
         ({rat_rs1_ind == 27} && entry_type_27)  |
         ({rat_rs1_ind == 28} && entry_type_28)  |
         ({rat_rs1_ind == 29} && entry_type_29)  |
         ({rat_rs1_ind == 30} && entry_type_30)  |
         ({rat_rs1_ind == 31} && entry_type_31) ;


assign rs2_rat_ready = rat_rs2_ind == 0 | 
         ({rat_rs2_ind == 1} && entry_type_1 && entry_ready_1) |
         ({rat_rs2_ind == 2} && entry_type_2 && entry_ready_2) |
         ({rat_rs2_ind == 3} && entry_type_3 && entry_ready_3) |
         ({rat_rs2_ind == 4} && entry_type_4 && entry_ready_4) |
         ({rat_rs2_ind == 5} && entry_type_5 && entry_ready_5) |
         ({rat_rs2_ind == 6} && entry_type_6 && entry_ready_6) |
         ({rat_rs2_ind == 7} && entry_type_7 && entry_ready_7) |
         ({rat_rs2_ind == 8} && entry_type_8 && entry_ready_8) |
         ({rat_rs2_ind == 9} && entry_type_9 && entry_ready_9) |
         ({rat_rs2_ind == 10} && entry_type_10 && entry_ready_10) |
         ({rat_rs2_ind == 11} && entry_type_11 && entry_ready_11) |
         ({rat_rs2_ind == 12} && entry_type_12 && entry_ready_12) |
         ({rat_rs2_ind == 13} && entry_type_13 && entry_ready_13) |
         ({rat_rs2_ind == 14} && entry_type_14 && entry_ready_14) |
         ({rat_rs2_ind == 15} && entry_type_15 && entry_ready_15) |
         ({rat_rs2_ind == 16} && entry_type_16 && entry_ready_16) |
         ({rat_rs2_ind == 17} && entry_type_17 && entry_ready_17) |
         ({rat_rs2_ind == 18} && entry_type_18 && entry_ready_18) |
         ({rat_rs2_ind == 19} && entry_type_19 && entry_ready_19) |
         ({rat_rs2_ind == 20} && entry_type_20 && entry_ready_20) |
         ({rat_rs2_ind == 21} && entry_type_21 && entry_ready_21) |
         ({rat_rs2_ind == 22} && entry_type_22 && entry_ready_22) |
         ({rat_rs2_ind == 23} && entry_type_23 && entry_ready_23) |
         ({rat_rs2_ind == 24} && entry_type_24 && entry_ready_24) |
         ({rat_rs2_ind == 25} && entry_type_25 && entry_ready_25) |
         ({rat_rs2_ind == 26} && entry_type_26 && entry_ready_26) |
         ({rat_rs2_ind == 27} && entry_type_27 && entry_ready_27) |
         ({rat_rs2_ind == 28} && entry_type_28 && entry_ready_28) |
         ({rat_rs2_ind == 29} && entry_type_29 && entry_ready_29) |
         ({rat_rs2_ind == 30} && entry_type_30 && entry_ready_30) |
         ({rat_rs2_ind == 31} && entry_type_31  && entry_ready_31) ;


assign rs2_rat_type = 
         ({rat_rs2_ind == 1} && entry_type_1)  |
         ({rat_rs2_ind == 2} && entry_type_2)  |
         ({rat_rs2_ind == 3} && entry_type_3)  |
         ({rat_rs2_ind == 4} && entry_type_4)  |
         ({rat_rs2_ind == 5} && entry_type_5)  |
         ({rat_rs2_ind == 6} && entry_type_6)  |
         ({rat_rs2_ind == 7} && entry_type_7)  |
         ({rat_rs2_ind == 8} && entry_type_8)  |
         ({rat_rs2_ind == 9} && entry_type_9)  |
         ({rat_rs2_ind == 10} && entry_type_10)  |
         ({rat_rs2_ind == 11} && entry_type_11)  |
         ({rat_rs2_ind == 12} && entry_type_12)  |
         ({rat_rs2_ind == 13} && entry_type_13)  |
         ({rat_rs2_ind == 14} && entry_type_14)  |
         ({rat_rs2_ind == 15} && entry_type_15)  |
         ({rat_rs2_ind == 16} && entry_type_16)  |
         ({rat_rs2_ind == 17} && entry_type_17)  |
         ({rat_rs2_ind == 18} && entry_type_18)  |
         ({rat_rs2_ind == 19} && entry_type_19)  |
         ({rat_rs2_ind == 20} && entry_type_20)  |
         ({rat_rs2_ind == 21} && entry_type_21)  |
         ({rat_rs2_ind == 22} && entry_type_22)  |
         ({rat_rs2_ind == 23} && entry_type_23)  |
         ({rat_rs2_ind == 24} && entry_type_24)  |
         ({rat_rs2_ind == 25} && entry_type_25)  |
         ({rat_rs2_ind == 26} && entry_type_26)  |
         ({rat_rs2_ind == 27} && entry_type_27)  |
         ({rat_rs2_ind == 28} && entry_type_28)  |
         ({rat_rs2_ind == 29} && entry_type_29)  |
         ({rat_rs2_ind == 30} && entry_type_30)  |
         ({rat_rs2_ind == 31} && entry_type_31) ;


assign rs1_index_map = 
         {(5+1){rat_rs1_ind == 1}} & entry_id_1 |
         {(5+1){rat_rs1_ind == 2}} & entry_id_2 |
         {(5+1){rat_rs1_ind == 3}} & entry_id_3 |
         {(5+1){rat_rs1_ind == 4}} & entry_id_4 |
         {(5+1){rat_rs1_ind == 5}} & entry_id_5 |
         {(5+1){rat_rs1_ind == 6}} & entry_id_6 |
         {(5+1){rat_rs1_ind == 7}} & entry_id_7 |
         {(5+1){rat_rs1_ind == 8}} & entry_id_8 |
         {(5+1){rat_rs1_ind == 9}} & entry_id_9 |
         {(5+1){rat_rs1_ind == 10}} & entry_id_10 |
         {(5+1){rat_rs1_ind == 11}} & entry_id_11 |
         {(5+1){rat_rs1_ind == 12}} & entry_id_12 |
         {(5+1){rat_rs1_ind == 13}} & entry_id_13 |
         {(5+1){rat_rs1_ind == 14}} & entry_id_14 |
         {(5+1){rat_rs1_ind == 15}} & entry_id_15 |
         {(5+1){rat_rs1_ind == 16}} & entry_id_16 |
         {(5+1){rat_rs1_ind == 17}} & entry_id_17 |
         {(5+1){rat_rs1_ind == 18}} & entry_id_18 |
         {(5+1){rat_rs1_ind == 19}} & entry_id_19 |
         {(5+1){rat_rs1_ind == 20}} & entry_id_20 |
         {(5+1){rat_rs1_ind == 21}} & entry_id_21 |
         {(5+1){rat_rs1_ind == 22}} & entry_id_22 |
         {(5+1){rat_rs1_ind == 23}} & entry_id_23 |
         {(5+1){rat_rs1_ind == 24}} & entry_id_24 |
         {(5+1){rat_rs1_ind == 25}} & entry_id_25 |
         {(5+1){rat_rs1_ind == 26}} & entry_id_26 |
         {(5+1){rat_rs1_ind == 27}} & entry_id_27 |
         {(5+1){rat_rs1_ind == 28}} & entry_id_28 |
         {(5+1){rat_rs1_ind == 29}} & entry_id_29 |
         {(5+1){rat_rs1_ind == 30}} & entry_id_30 |
         {(5+1){rat_rs1_ind == 31}} & entry_id_31;


assign rs2_index_map = 
         {(5+1){rat_rs2_ind == 1}} & entry_id_1 |
         {(5+1){rat_rs2_ind == 2}} & entry_id_2 |
         {(5+1){rat_rs2_ind == 3}} & entry_id_3 |
         {(5+1){rat_rs2_ind == 4}} & entry_id_4 |
         {(5+1){rat_rs2_ind == 5}} & entry_id_5 |
         {(5+1){rat_rs2_ind == 6}} & entry_id_6 |
         {(5+1){rat_rs2_ind == 7}} & entry_id_7 |
         {(5+1){rat_rs2_ind == 8}} & entry_id_8 |
         {(5+1){rat_rs2_ind == 9}} & entry_id_9 |
         {(5+1){rat_rs2_ind == 10}} & entry_id_10 |
         {(5+1){rat_rs2_ind == 11}} & entry_id_11 |
         {(5+1){rat_rs2_ind == 12}} & entry_id_12 |
         {(5+1){rat_rs2_ind == 13}} & entry_id_13 |
         {(5+1){rat_rs2_ind == 14}} & entry_id_14 |
         {(5+1){rat_rs2_ind == 15}} & entry_id_15 |
         {(5+1){rat_rs2_ind == 16}} & entry_id_16 |
         {(5+1){rat_rs2_ind == 17}} & entry_id_17 |
         {(5+1){rat_rs2_ind == 18}} & entry_id_18 |
         {(5+1){rat_rs2_ind == 19}} & entry_id_19 |
         {(5+1){rat_rs2_ind == 20}} & entry_id_20 |
         {(5+1){rat_rs2_ind == 21}} & entry_id_21 |
         {(5+1){rat_rs2_ind == 22}} & entry_id_22 |
         {(5+1){rat_rs2_ind == 23}} & entry_id_23 |
         {(5+1){rat_rs2_ind == 24}} & entry_id_24 |
         {(5+1){rat_rs2_ind == 25}} & entry_id_25 |
         {(5+1){rat_rs2_ind == 26}} & entry_id_26 |
         {(5+1){rat_rs2_ind == 27}} & entry_id_27 |
         {(5+1){rat_rs2_ind == 28}} & entry_id_28 |
         {(5+1){rat_rs2_ind == 29}} & entry_id_29 |
         {(5+1){rat_rs2_ind == 30}} & entry_id_30 |
         {(5+1){rat_rs2_ind == 31}} & entry_id_31;


// Retire Match
assign rs1_retire_match = ret_inst_id == rs1_index_map && ret_rd_req && rs1_rat_type;
assign rs2_retire_match = ret_inst_id == rs2_index_map && ret_rd_req && rs2_rat_type;

assign rs1_type = rs1_rat_type && ~rs1_retire_match;
assign rs2_type = rs2_rat_type && ~rs2_retire_match;

assign rat_rs1_map_nxt = rs1_type ? rs1_index_map : {{(5-5+1){0}},rat_rs1_ind};
assign rat_rs2_map_nxt = rs2_type ? rs2_index_map : {{(5-5+1){0}},rat_rs2_ind};

// assign rat_rd_map_nxt  = rat_rob_wprt;

// Function Unit Foward Match
assign rs1_fu_match = (rs1_rat_type && rs1_index_map == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) || 
                      (rs1_rat_type && rs1_index_map == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) || 
                      (rs1_rat_type && rs1_index_map == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);

assign rs2_fu_match = (rs2_rat_type && rs2_index_map == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) || 
                      (rs2_rat_type && rs2_index_map == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) || 
                      (rs2_rat_type && rs2_index_map == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);

assign rs1_ready = ~rs1_rat_type || 
                   (rs1_rat_type && rs1_rat_ready) ||
                   rs1_fu_match;

assign rs2_ready = ~rs2_rat_type || 
                   (rs2_rat_type && rs2_rat_ready) ||
                   rs2_fu_match;


wire rs1_stall_fu_match;
wire rs2_stall_fu_match;

assign rs1_stall_fu_match = (rat_rs1_type && rat_rs1_map == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) || 
                            (rat_rs1_type && rat_rs1_map == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) || 
                            (rat_rs1_type && rat_rs1_map == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);;

assign rs2_stall_fu_match = (rat_rs2_type && rat_rs2_map == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) || 
                            (rat_rs2_type && rat_rs2_map == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) || 
                            (rat_rs2_type && rat_rs2_map == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);;

wire rs1_stall_ret_match;
wire rs2_stall_ret_match;

assign rs1_stall_ret_match = ret_inst_id == rat_rs1_map && ret_rd_req && rs1_rat_type && ~isq_entry_wen;
assign rs2_stall_ret_match = ret_inst_id == rat_rs2_map && ret_rd_req && rs1_rat_type && ~isq_entry_wen;


wire rs1_ready_wen;
wire rs1_type_wen;

assign rs1_ready_wen = (rs1_stall_fu_match && ~isq_entry_wen) || rs1_retire_match || isq_entry_wen;
assign rs1_type_wen  = rs1_stall_ret_match || isq_entry_wen;

wire rs2_ready_wen;
wire rs2_type_wen;

assign rs2_ready_wen = (rs1_stall_fu_match && ~isq_entry_wen) || rs2_retire_match || isq_entry_wen;
assign rs2_type_wen  = rs1_stall_ret_match || isq_entry_wen;

assign rat_rs1_type_nxt  = rs1_type && ~rs1_stall_ret_match;
assign rat_rs2_type_nxt  = rs2_type && ~rs2_stall_ret_match;

assign rat_rs1_ready_nxt = rs1_ready || (rs1_stall_fu_match && ~isq_entry_wen);
assign rat_rs2_ready_nxt = rs2_ready || (rs2_stall_fu_match && ~isq_entry_wen);


// Instruction Retire Operation
// Entry Write Enable
assign entry_req_wen_0 = rat_rd_vld && rat_rd_ind == 0;
assign entry_req_wen_1 = rat_rd_vld && rat_rd_ind == 1;
assign entry_req_wen_2 = rat_rd_vld && rat_rd_ind == 2;
assign entry_req_wen_3 = rat_rd_vld && rat_rd_ind == 3;
assign entry_req_wen_4 = rat_rd_vld && rat_rd_ind == 4;
assign entry_req_wen_5 = rat_rd_vld && rat_rd_ind == 5;
assign entry_req_wen_6 = rat_rd_vld && rat_rd_ind == 6;
assign entry_req_wen_7 = rat_rd_vld && rat_rd_ind == 7;
assign entry_req_wen_8 = rat_rd_vld && rat_rd_ind == 8;
assign entry_req_wen_9 = rat_rd_vld && rat_rd_ind == 9;
assign entry_req_wen_10 = rat_rd_vld && rat_rd_ind == 10;
assign entry_req_wen_11 = rat_rd_vld && rat_rd_ind == 11;
assign entry_req_wen_12 = rat_rd_vld && rat_rd_ind == 12;
assign entry_req_wen_13 = rat_rd_vld && rat_rd_ind == 13;
assign entry_req_wen_14 = rat_rd_vld && rat_rd_ind == 14;
assign entry_req_wen_15 = rat_rd_vld && rat_rd_ind == 15;
assign entry_req_wen_16 = rat_rd_vld && rat_rd_ind == 16;
assign entry_req_wen_17 = rat_rd_vld && rat_rd_ind == 17;
assign entry_req_wen_18 = rat_rd_vld && rat_rd_ind == 18;
assign entry_req_wen_19 = rat_rd_vld && rat_rd_ind == 19;
assign entry_req_wen_20 = rat_rd_vld && rat_rd_ind == 20;
assign entry_req_wen_21 = rat_rd_vld && rat_rd_ind == 21;
assign entry_req_wen_22 = rat_rd_vld && rat_rd_ind == 22;
assign entry_req_wen_23 = rat_rd_vld && rat_rd_ind == 23;
assign entry_req_wen_24 = rat_rd_vld && rat_rd_ind == 24;
assign entry_req_wen_25 = rat_rd_vld && rat_rd_ind == 25;
assign entry_req_wen_26 = rat_rd_vld && rat_rd_ind == 26;
assign entry_req_wen_27 = rat_rd_vld && rat_rd_ind == 27;
assign entry_req_wen_28 = rat_rd_vld && rat_rd_ind == 28;
assign entry_req_wen_29 = rat_rd_vld && rat_rd_ind == 29;
assign entry_req_wen_30 = rat_rd_vld && rat_rd_ind == 30;
assign entry_req_wen_31 = rat_rd_vld && rat_rd_ind == 31;

assign entry_ready_wen_0 = entry_req_wen_0 || 
                         (entry_type_0 && entry_id_0 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_0 && entry_id_0 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_0 && entry_id_0 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_1 = entry_req_wen_1 || 
                         (entry_type_1 && entry_id_1 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_1 && entry_id_1 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_1 && entry_id_1 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_2 = entry_req_wen_2 || 
                         (entry_type_2 && entry_id_2 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_2 && entry_id_2 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_2 && entry_id_2 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_3 = entry_req_wen_3 || 
                         (entry_type_3 && entry_id_3 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_3 && entry_id_3 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_3 && entry_id_3 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_4 = entry_req_wen_4 || 
                         (entry_type_4 && entry_id_4 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_4 && entry_id_4 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_4 && entry_id_4 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_5 = entry_req_wen_5 || 
                         (entry_type_5 && entry_id_5 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_5 && entry_id_5 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_5 && entry_id_5 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_6 = entry_req_wen_6 || 
                         (entry_type_6 && entry_id_6 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_6 && entry_id_6 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_6 && entry_id_6 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_7 = entry_req_wen_7 || 
                         (entry_type_7 && entry_id_7 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_7 && entry_id_7 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_7 && entry_id_7 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_8 = entry_req_wen_8 || 
                         (entry_type_8 && entry_id_8 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_8 && entry_id_8 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_8 && entry_id_8 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_9 = entry_req_wen_9 || 
                         (entry_type_9 && entry_id_9 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_9 && entry_id_9 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_9 && entry_id_9 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_10 = entry_req_wen_10 || 
                         (entry_type_10 && entry_id_10 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_10 && entry_id_10 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_10 && entry_id_10 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_11 = entry_req_wen_11 || 
                         (entry_type_11 && entry_id_11 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_11 && entry_id_11 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_11 && entry_id_11 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_12 = entry_req_wen_12 || 
                         (entry_type_12 && entry_id_12 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_12 && entry_id_12 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_12 && entry_id_12 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_13 = entry_req_wen_13 || 
                         (entry_type_13 && entry_id_13 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_13 && entry_id_13 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_13 && entry_id_13 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_14 = entry_req_wen_14 || 
                         (entry_type_14 && entry_id_14 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_14 && entry_id_14 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_14 && entry_id_14 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_15 = entry_req_wen_15 || 
                         (entry_type_15 && entry_id_15 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_15 && entry_id_15 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_15 && entry_id_15 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_16 = entry_req_wen_16 || 
                         (entry_type_16 && entry_id_16 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_16 && entry_id_16 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_16 && entry_id_16 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_17 = entry_req_wen_17 || 
                         (entry_type_17 && entry_id_17 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_17 && entry_id_17 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_17 && entry_id_17 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_18 = entry_req_wen_18 || 
                         (entry_type_18 && entry_id_18 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_18 && entry_id_18 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_18 && entry_id_18 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_19 = entry_req_wen_19 || 
                         (entry_type_19 && entry_id_19 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_19 && entry_id_19 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_19 && entry_id_19 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_20 = entry_req_wen_20 || 
                         (entry_type_20 && entry_id_20 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_20 && entry_id_20 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_20 && entry_id_20 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_21 = entry_req_wen_21 || 
                         (entry_type_21 && entry_id_21 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_21 && entry_id_21 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_21 && entry_id_21 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_22 = entry_req_wen_22 || 
                         (entry_type_22 && entry_id_22 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_22 && entry_id_22 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_22 && entry_id_22 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_23 = entry_req_wen_23 || 
                         (entry_type_23 && entry_id_23 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_23 && entry_id_23 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_23 && entry_id_23 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_24 = entry_req_wen_24 || 
                         (entry_type_24 && entry_id_24 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_24 && entry_id_24 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_24 && entry_id_24 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_25 = entry_req_wen_25 || 
                         (entry_type_25 && entry_id_25 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_25 && entry_id_25 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_25 && entry_id_25 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_26 = entry_req_wen_26 || 
                         (entry_type_26 && entry_id_26 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_26 && entry_id_26 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_26 && entry_id_26 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_27 = entry_req_wen_27 || 
                         (entry_type_27 && entry_id_27 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_27 && entry_id_27 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_27 && entry_id_27 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_28 = entry_req_wen_28 || 
                         (entry_type_28 && entry_id_28 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_28 && entry_id_28 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_28 && entry_id_28 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_29 = entry_req_wen_29 || 
                         (entry_type_29 && entry_id_29 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_29 && entry_id_29 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_29 && entry_id_29 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_30 = entry_req_wen_30 || 
                         (entry_type_30 && entry_id_30 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_30 && entry_id_30 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_30 && entry_id_30 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);
assign entry_ready_wen_31 = entry_req_wen_31 || 
                         (entry_type_31 && entry_id_31 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                         (entry_type_31 && entry_id_31 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                         (entry_type_31 && entry_id_31 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld);

assign entry_type_wen_0 = entry_req_wen_0 || ret_flush_rles || 
                         (ret_rd_req && entry_id_0 == ret_inst_id && entry_type_0);
assign entry_type_wen_1 = entry_req_wen_1 || ret_flush_rles || 
                         (ret_rd_req && entry_id_1 == ret_inst_id && entry_type_1);
assign entry_type_wen_2 = entry_req_wen_2 || ret_flush_rles || 
                         (ret_rd_req && entry_id_2 == ret_inst_id && entry_type_2);
assign entry_type_wen_3 = entry_req_wen_3 || ret_flush_rles || 
                         (ret_rd_req && entry_id_3 == ret_inst_id && entry_type_3);
assign entry_type_wen_4 = entry_req_wen_4 || ret_flush_rles || 
                         (ret_rd_req && entry_id_4 == ret_inst_id && entry_type_4);
assign entry_type_wen_5 = entry_req_wen_5 || ret_flush_rles || 
                         (ret_rd_req && entry_id_5 == ret_inst_id && entry_type_5);
assign entry_type_wen_6 = entry_req_wen_6 || ret_flush_rles || 
                         (ret_rd_req && entry_id_6 == ret_inst_id && entry_type_6);
assign entry_type_wen_7 = entry_req_wen_7 || ret_flush_rles || 
                         (ret_rd_req && entry_id_7 == ret_inst_id && entry_type_7);
assign entry_type_wen_8 = entry_req_wen_8 || ret_flush_rles || 
                         (ret_rd_req && entry_id_8 == ret_inst_id && entry_type_8);
assign entry_type_wen_9 = entry_req_wen_9 || ret_flush_rles || 
                         (ret_rd_req && entry_id_9 == ret_inst_id && entry_type_9);
assign entry_type_wen_10 = entry_req_wen_10 || ret_flush_rles || 
                         (ret_rd_req && entry_id_10 == ret_inst_id && entry_type_10);
assign entry_type_wen_11 = entry_req_wen_11 || ret_flush_rles || 
                         (ret_rd_req && entry_id_11 == ret_inst_id && entry_type_11);
assign entry_type_wen_12 = entry_req_wen_12 || ret_flush_rles || 
                         (ret_rd_req && entry_id_12 == ret_inst_id && entry_type_12);
assign entry_type_wen_13 = entry_req_wen_13 || ret_flush_rles || 
                         (ret_rd_req && entry_id_13 == ret_inst_id && entry_type_13);
assign entry_type_wen_14 = entry_req_wen_14 || ret_flush_rles || 
                         (ret_rd_req && entry_id_14 == ret_inst_id && entry_type_14);
assign entry_type_wen_15 = entry_req_wen_15 || ret_flush_rles || 
                         (ret_rd_req && entry_id_15 == ret_inst_id && entry_type_15);
assign entry_type_wen_16 = entry_req_wen_16 || ret_flush_rles || 
                         (ret_rd_req && entry_id_16 == ret_inst_id && entry_type_16);
assign entry_type_wen_17 = entry_req_wen_17 || ret_flush_rles || 
                         (ret_rd_req && entry_id_17 == ret_inst_id && entry_type_17);
assign entry_type_wen_18 = entry_req_wen_18 || ret_flush_rles || 
                         (ret_rd_req && entry_id_18 == ret_inst_id && entry_type_18);
assign entry_type_wen_19 = entry_req_wen_19 || ret_flush_rles || 
                         (ret_rd_req && entry_id_19 == ret_inst_id && entry_type_19);
assign entry_type_wen_20 = entry_req_wen_20 || ret_flush_rles || 
                         (ret_rd_req && entry_id_20 == ret_inst_id && entry_type_20);
assign entry_type_wen_21 = entry_req_wen_21 || ret_flush_rles || 
                         (ret_rd_req && entry_id_21 == ret_inst_id && entry_type_21);
assign entry_type_wen_22 = entry_req_wen_22 || ret_flush_rles || 
                         (ret_rd_req && entry_id_22 == ret_inst_id && entry_type_22);
assign entry_type_wen_23 = entry_req_wen_23 || ret_flush_rles || 
                         (ret_rd_req && entry_id_23 == ret_inst_id && entry_type_23);
assign entry_type_wen_24 = entry_req_wen_24 || ret_flush_rles || 
                         (ret_rd_req && entry_id_24 == ret_inst_id && entry_type_24);
assign entry_type_wen_25 = entry_req_wen_25 || ret_flush_rles || 
                         (ret_rd_req && entry_id_25 == ret_inst_id && entry_type_25);
assign entry_type_wen_26 = entry_req_wen_26 || ret_flush_rles || 
                         (ret_rd_req && entry_id_26 == ret_inst_id && entry_type_26);
assign entry_type_wen_27 = entry_req_wen_27 || ret_flush_rles || 
                         (ret_rd_req && entry_id_27 == ret_inst_id && entry_type_27);
assign entry_type_wen_28 = entry_req_wen_28 || ret_flush_rles || 
                         (ret_rd_req && entry_id_28 == ret_inst_id && entry_type_28);
assign entry_type_wen_29 = entry_req_wen_29 || ret_flush_rles || 
                         (ret_rd_req && entry_id_29 == ret_inst_id && entry_type_29);
assign entry_type_wen_30 = entry_req_wen_30 || ret_flush_rles || 
                         (ret_rd_req && entry_id_30 == ret_inst_id && entry_type_30);
assign entry_type_wen_31 = entry_req_wen_31 || ret_flush_rles || 
                         (ret_rd_req && entry_id_31 == ret_inst_id && entry_type_31);

assign entry_id_wen_0 = entry_req_wen_0;
assign entry_id_wen_1 = entry_req_wen_1;
assign entry_id_wen_2 = entry_req_wen_2;
assign entry_id_wen_3 = entry_req_wen_3;
assign entry_id_wen_4 = entry_req_wen_4;
assign entry_id_wen_5 = entry_req_wen_5;
assign entry_id_wen_6 = entry_req_wen_6;
assign entry_id_wen_7 = entry_req_wen_7;
assign entry_id_wen_8 = entry_req_wen_8;
assign entry_id_wen_9 = entry_req_wen_9;
assign entry_id_wen_10 = entry_req_wen_10;
assign entry_id_wen_11 = entry_req_wen_11;
assign entry_id_wen_12 = entry_req_wen_12;
assign entry_id_wen_13 = entry_req_wen_13;
assign entry_id_wen_14 = entry_req_wen_14;
assign entry_id_wen_15 = entry_req_wen_15;
assign entry_id_wen_16 = entry_req_wen_16;
assign entry_id_wen_17 = entry_req_wen_17;
assign entry_id_wen_18 = entry_req_wen_18;
assign entry_id_wen_19 = entry_req_wen_19;
assign entry_id_wen_20 = entry_req_wen_20;
assign entry_id_wen_21 = entry_req_wen_21;
assign entry_id_wen_22 = entry_req_wen_22;
assign entry_id_wen_23 = entry_req_wen_23;
assign entry_id_wen_24 = entry_req_wen_24;
assign entry_id_wen_25 = entry_req_wen_25;
assign entry_id_wen_26 = entry_req_wen_26;
assign entry_id_wen_27 = entry_req_wen_27;
assign entry_id_wen_28 = entry_req_wen_28;
assign entry_id_wen_29 = entry_req_wen_29;
assign entry_id_wen_30 = entry_req_wen_30;
assign entry_id_wen_31 = entry_req_wen_31;
// Entry D Ports
assign entry_ready_nxt_0 = ~entry_req_wen_0 && 
                         ((entry_type_0 && entry_id_0 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_0 && entry_id_0 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_0 && entry_id_0 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_1 = ~entry_req_wen_1 && 
                         ((entry_type_1 && entry_id_1 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_1 && entry_id_1 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_1 && entry_id_1 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_2 = ~entry_req_wen_2 && 
                         ((entry_type_2 && entry_id_2 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_2 && entry_id_2 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_2 && entry_id_2 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_3 = ~entry_req_wen_3 && 
                         ((entry_type_3 && entry_id_3 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_3 && entry_id_3 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_3 && entry_id_3 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_4 = ~entry_req_wen_4 && 
                         ((entry_type_4 && entry_id_4 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_4 && entry_id_4 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_4 && entry_id_4 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_5 = ~entry_req_wen_5 && 
                         ((entry_type_5 && entry_id_5 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_5 && entry_id_5 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_5 && entry_id_5 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_6 = ~entry_req_wen_6 && 
                         ((entry_type_6 && entry_id_6 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_6 && entry_id_6 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_6 && entry_id_6 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_7 = ~entry_req_wen_7 && 
                         ((entry_type_7 && entry_id_7 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_7 && entry_id_7 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_7 && entry_id_7 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_8 = ~entry_req_wen_8 && 
                         ((entry_type_8 && entry_id_8 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_8 && entry_id_8 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_8 && entry_id_8 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_9 = ~entry_req_wen_9 && 
                         ((entry_type_9 && entry_id_9 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_9 && entry_id_9 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_9 && entry_id_9 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_10 = ~entry_req_wen_10 && 
                         ((entry_type_10 && entry_id_10 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_10 && entry_id_10 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_10 && entry_id_10 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_11 = ~entry_req_wen_11 && 
                         ((entry_type_11 && entry_id_11 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_11 && entry_id_11 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_11 && entry_id_11 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_12 = ~entry_req_wen_12 && 
                         ((entry_type_12 && entry_id_12 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_12 && entry_id_12 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_12 && entry_id_12 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_13 = ~entry_req_wen_13 && 
                         ((entry_type_13 && entry_id_13 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_13 && entry_id_13 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_13 && entry_id_13 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_14 = ~entry_req_wen_14 && 
                         ((entry_type_14 && entry_id_14 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_14 && entry_id_14 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_14 && entry_id_14 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_15 = ~entry_req_wen_15 && 
                         ((entry_type_15 && entry_id_15 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_15 && entry_id_15 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_15 && entry_id_15 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_16 = ~entry_req_wen_16 && 
                         ((entry_type_16 && entry_id_16 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_16 && entry_id_16 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_16 && entry_id_16 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_17 = ~entry_req_wen_17 && 
                         ((entry_type_17 && entry_id_17 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_17 && entry_id_17 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_17 && entry_id_17 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_18 = ~entry_req_wen_18 && 
                         ((entry_type_18 && entry_id_18 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_18 && entry_id_18 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_18 && entry_id_18 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_19 = ~entry_req_wen_19 && 
                         ((entry_type_19 && entry_id_19 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_19 && entry_id_19 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_19 && entry_id_19 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_20 = ~entry_req_wen_20 && 
                         ((entry_type_20 && entry_id_20 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_20 && entry_id_20 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_20 && entry_id_20 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_21 = ~entry_req_wen_21 && 
                         ((entry_type_21 && entry_id_21 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_21 && entry_id_21 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_21 && entry_id_21 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_22 = ~entry_req_wen_22 && 
                         ((entry_type_22 && entry_id_22 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_22 && entry_id_22 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_22 && entry_id_22 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_23 = ~entry_req_wen_23 && 
                         ((entry_type_23 && entry_id_23 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_23 && entry_id_23 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_23 && entry_id_23 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_24 = ~entry_req_wen_24 && 
                         ((entry_type_24 && entry_id_24 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_24 && entry_id_24 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_24 && entry_id_24 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_25 = ~entry_req_wen_25 && 
                         ((entry_type_25 && entry_id_25 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_25 && entry_id_25 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_25 && entry_id_25 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_26 = ~entry_req_wen_26 && 
                         ((entry_type_26 && entry_id_26 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_26 && entry_id_26 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_26 && entry_id_26 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_27 = ~entry_req_wen_27 && 
                         ((entry_type_27 && entry_id_27 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_27 && entry_id_27 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_27 && entry_id_27 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_28 = ~entry_req_wen_28 && 
                         ((entry_type_28 && entry_id_28 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_28 && entry_id_28 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_28 && entry_id_28 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_29 = ~entry_req_wen_29 && 
                         ((entry_type_29 && entry_id_29 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_29 && entry_id_29 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_29 && entry_id_29 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_30 = ~entry_req_wen_30 && 
                         ((entry_type_30 && entry_id_30 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_30 && entry_id_30 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_30 && entry_id_30 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));
assign entry_ready_nxt_31 = ~entry_req_wen_31 && 
                         ((entry_type_31 && entry_id_31 == alu_fwd_inst_id && alu_fwd_rd_vld && alu_fwd_vld) ||
                          (entry_type_31 && entry_id_31 == bru_fwd_inst_id && bru_fwd_rd_vld && bru_fwd_vld) ||
                          (entry_type_31 && entry_id_31 == lsu_fwd_inst_id && lsu_fwd_rd_vld && lsu_fwd_vld));

assign entry_type_nxt_0 = ~ret_flush_rles && (entry_req_wen_0 ||
                         (ret_rd_req && entry_id_0 == ret_inst_id && entry_type_0));
assign entry_type_nxt_1 = ~ret_flush_rles && (entry_req_wen_1 ||
                         (ret_rd_req && entry_id_1 == ret_inst_id && entry_type_1));
assign entry_type_nxt_2 = ~ret_flush_rles && (entry_req_wen_2 ||
                         (ret_rd_req && entry_id_2 == ret_inst_id && entry_type_2));
assign entry_type_nxt_3 = ~ret_flush_rles && (entry_req_wen_3 ||
                         (ret_rd_req && entry_id_3 == ret_inst_id && entry_type_3));
assign entry_type_nxt_4 = ~ret_flush_rles && (entry_req_wen_4 ||
                         (ret_rd_req && entry_id_4 == ret_inst_id && entry_type_4));
assign entry_type_nxt_5 = ~ret_flush_rles && (entry_req_wen_5 ||
                         (ret_rd_req && entry_id_5 == ret_inst_id && entry_type_5));
assign entry_type_nxt_6 = ~ret_flush_rles && (entry_req_wen_6 ||
                         (ret_rd_req && entry_id_6 == ret_inst_id && entry_type_6));
assign entry_type_nxt_7 = ~ret_flush_rles && (entry_req_wen_7 ||
                         (ret_rd_req && entry_id_7 == ret_inst_id && entry_type_7));
assign entry_type_nxt_8 = ~ret_flush_rles && (entry_req_wen_8 ||
                         (ret_rd_req && entry_id_8 == ret_inst_id && entry_type_8));
assign entry_type_nxt_9 = ~ret_flush_rles && (entry_req_wen_9 ||
                         (ret_rd_req && entry_id_9 == ret_inst_id && entry_type_9));
assign entry_type_nxt_10 = ~ret_flush_rles && (entry_req_wen_10 ||
                         (ret_rd_req && entry_id_10 == ret_inst_id && entry_type_10));
assign entry_type_nxt_11 = ~ret_flush_rles && (entry_req_wen_11 ||
                         (ret_rd_req && entry_id_11 == ret_inst_id && entry_type_11));
assign entry_type_nxt_12 = ~ret_flush_rles && (entry_req_wen_12 ||
                         (ret_rd_req && entry_id_12 == ret_inst_id && entry_type_12));
assign entry_type_nxt_13 = ~ret_flush_rles && (entry_req_wen_13 ||
                         (ret_rd_req && entry_id_13 == ret_inst_id && entry_type_13));
assign entry_type_nxt_14 = ~ret_flush_rles && (entry_req_wen_14 ||
                         (ret_rd_req && entry_id_14 == ret_inst_id && entry_type_14));
assign entry_type_nxt_15 = ~ret_flush_rles && (entry_req_wen_15 ||
                         (ret_rd_req && entry_id_15 == ret_inst_id && entry_type_15));
assign entry_type_nxt_16 = ~ret_flush_rles && (entry_req_wen_16 ||
                         (ret_rd_req && entry_id_16 == ret_inst_id && entry_type_16));
assign entry_type_nxt_17 = ~ret_flush_rles && (entry_req_wen_17 ||
                         (ret_rd_req && entry_id_17 == ret_inst_id && entry_type_17));
assign entry_type_nxt_18 = ~ret_flush_rles && (entry_req_wen_18 ||
                         (ret_rd_req && entry_id_18 == ret_inst_id && entry_type_18));
assign entry_type_nxt_19 = ~ret_flush_rles && (entry_req_wen_19 ||
                         (ret_rd_req && entry_id_19 == ret_inst_id && entry_type_19));
assign entry_type_nxt_20 = ~ret_flush_rles && (entry_req_wen_20 ||
                         (ret_rd_req && entry_id_20 == ret_inst_id && entry_type_20));
assign entry_type_nxt_21 = ~ret_flush_rles && (entry_req_wen_21 ||
                         (ret_rd_req && entry_id_21 == ret_inst_id && entry_type_21));
assign entry_type_nxt_22 = ~ret_flush_rles && (entry_req_wen_22 ||
                         (ret_rd_req && entry_id_22 == ret_inst_id && entry_type_22));
assign entry_type_nxt_23 = ~ret_flush_rles && (entry_req_wen_23 ||
                         (ret_rd_req && entry_id_23 == ret_inst_id && entry_type_23));
assign entry_type_nxt_24 = ~ret_flush_rles && (entry_req_wen_24 ||
                         (ret_rd_req && entry_id_24 == ret_inst_id && entry_type_24));
assign entry_type_nxt_25 = ~ret_flush_rles && (entry_req_wen_25 ||
                         (ret_rd_req && entry_id_25 == ret_inst_id && entry_type_25));
assign entry_type_nxt_26 = ~ret_flush_rles && (entry_req_wen_26 ||
                         (ret_rd_req && entry_id_26 == ret_inst_id && entry_type_26));
assign entry_type_nxt_27 = ~ret_flush_rles && (entry_req_wen_27 ||
                         (ret_rd_req && entry_id_27 == ret_inst_id && entry_type_27));
assign entry_type_nxt_28 = ~ret_flush_rles && (entry_req_wen_28 ||
                         (ret_rd_req && entry_id_28 == ret_inst_id && entry_type_28));
assign entry_type_nxt_29 = ~ret_flush_rles && (entry_req_wen_29 ||
                         (ret_rd_req && entry_id_29 == ret_inst_id && entry_type_29));
assign entry_type_nxt_30 = ~ret_flush_rles && (entry_req_wen_30 ||
                         (ret_rd_req && entry_id_30 == ret_inst_id && entry_type_30));
assign entry_type_nxt_31 = ~ret_flush_rles && (entry_req_wen_31 ||
                         (ret_rd_req && entry_id_31 == ret_inst_id && entry_type_31));
assign entry_id_nxt_0 = rat_rob_wprt;
assign entry_id_nxt_1 = rat_rob_wprt;
assign entry_id_nxt_2 = rat_rob_wprt;
assign entry_id_nxt_3 = rat_rob_wprt;
assign entry_id_nxt_4 = rat_rob_wprt;
assign entry_id_nxt_5 = rat_rob_wprt;
assign entry_id_nxt_6 = rat_rob_wprt;
assign entry_id_nxt_7 = rat_rob_wprt;
assign entry_id_nxt_8 = rat_rob_wprt;
assign entry_id_nxt_9 = rat_rob_wprt;
assign entry_id_nxt_10 = rat_rob_wprt;
assign entry_id_nxt_11 = rat_rob_wprt;
assign entry_id_nxt_12 = rat_rob_wprt;
assign entry_id_nxt_13 = rat_rob_wprt;
assign entry_id_nxt_14 = rat_rob_wprt;
assign entry_id_nxt_15 = rat_rob_wprt;
assign entry_id_nxt_16 = rat_rob_wprt;
assign entry_id_nxt_17 = rat_rob_wprt;
assign entry_id_nxt_18 = rat_rob_wprt;
assign entry_id_nxt_19 = rat_rob_wprt;
assign entry_id_nxt_20 = rat_rob_wprt;
assign entry_id_nxt_21 = rat_rob_wprt;
assign entry_id_nxt_22 = rat_rob_wprt;
assign entry_id_nxt_23 = rat_rob_wprt;
assign entry_id_nxt_24 = rat_rob_wprt;
assign entry_id_nxt_25 = rat_rob_wprt;
assign entry_id_nxt_26 = rat_rob_wprt;
assign entry_id_nxt_27 = rat_rob_wprt;
assign entry_id_nxt_28 = rat_rob_wprt;
assign entry_id_nxt_29 = rat_rob_wprt;
assign entry_id_nxt_30 = rat_rob_wprt;
assign entry_id_nxt_31 = rat_rob_wprt;

//Port DFFs
dffr #(.DW(5+1)) rat_rs1_map_ff  (clk,rst_n,isq_entry_wen,rat_rs1_map_nxt   ,rat_rs1_map  ); 
dffr #(.DW(1)              ) rat_rs1_type_ff (clk,rst_n,rs1_type_wen ,rat_rs1_type_nxt  ,rat_rs1_type );  
dffr #(.DW(1)              ) rat_rs1_ready_ff(clk,rst_n,rs1_ready_wen,rat_rs1_ready_nxt ,rat_rs1_ready);   
dffr #(.DW(5+1)) rat_rs2_map_ff  (clk,rst_n,isq_entry_wen,rat_rs2_map_nxt   ,rat_rs2_map  ); 
dffr #(.DW(1)              ) rat_rs2_type_ff (clk,rst_n,rs2_type_wen ,rat_rs2_type_nxt  ,rat_rs2_type );  
dffr #(.DW(1)              ) rat_rs2_ready_ff(clk,rst_n,rs2_ready_wen,rat_rs2_ready_nxt ,rat_rs2_ready);   

//RAT DFFs
dffr #(.DW(1)              ) entry_ready_ff_0(clk,rst_n,entry_ready_wen_0,entry_ready_nxt_0,entry_ready_0);
dffr #(.DW(1)              ) entry_type_ff_0 (clk,rst_n,entry_type_wen_0 ,entry_type_nxt_0 ,entry_type_0 );
dffr #(.DW(5+1)) entry_id_ff_0   (clk,rst_n,entry_id_wen_0   ,entry_id_nxt_0   ,entry_id_0   );

dffr #(.DW(1)              ) entry_ready_ff_1(clk,rst_n,entry_ready_wen_1,entry_ready_nxt_1,entry_ready_1);
dffr #(.DW(1)              ) entry_type_ff_1 (clk,rst_n,entry_type_wen_1 ,entry_type_nxt_1 ,entry_type_1 );
dffr #(.DW(5+1)) entry_id_ff_1   (clk,rst_n,entry_id_wen_1   ,entry_id_nxt_1   ,entry_id_1   );

dffr #(.DW(1)              ) entry_ready_ff_2(clk,rst_n,entry_ready_wen_2,entry_ready_nxt_2,entry_ready_2);
dffr #(.DW(1)              ) entry_type_ff_2 (clk,rst_n,entry_type_wen_2 ,entry_type_nxt_2 ,entry_type_2 );
dffr #(.DW(5+1)) entry_id_ff_2   (clk,rst_n,entry_id_wen_2   ,entry_id_nxt_2   ,entry_id_2   );

dffr #(.DW(1)              ) entry_ready_ff_3(clk,rst_n,entry_ready_wen_3,entry_ready_nxt_3,entry_ready_3);
dffr #(.DW(1)              ) entry_type_ff_3 (clk,rst_n,entry_type_wen_3 ,entry_type_nxt_3 ,entry_type_3 );
dffr #(.DW(5+1)) entry_id_ff_3   (clk,rst_n,entry_id_wen_3   ,entry_id_nxt_3   ,entry_id_3   );

dffr #(.DW(1)              ) entry_ready_ff_4(clk,rst_n,entry_ready_wen_4,entry_ready_nxt_4,entry_ready_4);
dffr #(.DW(1)              ) entry_type_ff_4 (clk,rst_n,entry_type_wen_4 ,entry_type_nxt_4 ,entry_type_4 );
dffr #(.DW(5+1)) entry_id_ff_4   (clk,rst_n,entry_id_wen_4   ,entry_id_nxt_4   ,entry_id_4   );

dffr #(.DW(1)              ) entry_ready_ff_5(clk,rst_n,entry_ready_wen_5,entry_ready_nxt_5,entry_ready_5);
dffr #(.DW(1)              ) entry_type_ff_5 (clk,rst_n,entry_type_wen_5 ,entry_type_nxt_5 ,entry_type_5 );
dffr #(.DW(5+1)) entry_id_ff_5   (clk,rst_n,entry_id_wen_5   ,entry_id_nxt_5   ,entry_id_5   );

dffr #(.DW(1)              ) entry_ready_ff_6(clk,rst_n,entry_ready_wen_6,entry_ready_nxt_6,entry_ready_6);
dffr #(.DW(1)              ) entry_type_ff_6 (clk,rst_n,entry_type_wen_6 ,entry_type_nxt_6 ,entry_type_6 );
dffr #(.DW(5+1)) entry_id_ff_6   (clk,rst_n,entry_id_wen_6   ,entry_id_nxt_6   ,entry_id_6   );

dffr #(.DW(1)              ) entry_ready_ff_7(clk,rst_n,entry_ready_wen_7,entry_ready_nxt_7,entry_ready_7);
dffr #(.DW(1)              ) entry_type_ff_7 (clk,rst_n,entry_type_wen_7 ,entry_type_nxt_7 ,entry_type_7 );
dffr #(.DW(5+1)) entry_id_ff_7   (clk,rst_n,entry_id_wen_7   ,entry_id_nxt_7   ,entry_id_7   );

dffr #(.DW(1)              ) entry_ready_ff_8(clk,rst_n,entry_ready_wen_8,entry_ready_nxt_8,entry_ready_8);
dffr #(.DW(1)              ) entry_type_ff_8 (clk,rst_n,entry_type_wen_8 ,entry_type_nxt_8 ,entry_type_8 );
dffr #(.DW(5+1)) entry_id_ff_8   (clk,rst_n,entry_id_wen_8   ,entry_id_nxt_8   ,entry_id_8   );

dffr #(.DW(1)              ) entry_ready_ff_9(clk,rst_n,entry_ready_wen_9,entry_ready_nxt_9,entry_ready_9);
dffr #(.DW(1)              ) entry_type_ff_9 (clk,rst_n,entry_type_wen_9 ,entry_type_nxt_9 ,entry_type_9 );
dffr #(.DW(5+1)) entry_id_ff_9   (clk,rst_n,entry_id_wen_9   ,entry_id_nxt_9   ,entry_id_9   );

dffr #(.DW(1)              ) entry_ready_ff_10(clk,rst_n,entry_ready_wen_10,entry_ready_nxt_10,entry_ready_10);
dffr #(.DW(1)              ) entry_type_ff_10 (clk,rst_n,entry_type_wen_10 ,entry_type_nxt_10 ,entry_type_10 );
dffr #(.DW(5+1)) entry_id_ff_10   (clk,rst_n,entry_id_wen_10   ,entry_id_nxt_10   ,entry_id_10   );

dffr #(.DW(1)              ) entry_ready_ff_11(clk,rst_n,entry_ready_wen_11,entry_ready_nxt_11,entry_ready_11);
dffr #(.DW(1)              ) entry_type_ff_11 (clk,rst_n,entry_type_wen_11 ,entry_type_nxt_11 ,entry_type_11 );
dffr #(.DW(5+1)) entry_id_ff_11   (clk,rst_n,entry_id_wen_11   ,entry_id_nxt_11   ,entry_id_11   );

dffr #(.DW(1)              ) entry_ready_ff_12(clk,rst_n,entry_ready_wen_12,entry_ready_nxt_12,entry_ready_12);
dffr #(.DW(1)              ) entry_type_ff_12 (clk,rst_n,entry_type_wen_12 ,entry_type_nxt_12 ,entry_type_12 );
dffr #(.DW(5+1)) entry_id_ff_12   (clk,rst_n,entry_id_wen_12   ,entry_id_nxt_12   ,entry_id_12   );

dffr #(.DW(1)              ) entry_ready_ff_13(clk,rst_n,entry_ready_wen_13,entry_ready_nxt_13,entry_ready_13);
dffr #(.DW(1)              ) entry_type_ff_13 (clk,rst_n,entry_type_wen_13 ,entry_type_nxt_13 ,entry_type_13 );
dffr #(.DW(5+1)) entry_id_ff_13   (clk,rst_n,entry_id_wen_13   ,entry_id_nxt_13   ,entry_id_13   );

dffr #(.DW(1)              ) entry_ready_ff_14(clk,rst_n,entry_ready_wen_14,entry_ready_nxt_14,entry_ready_14);
dffr #(.DW(1)              ) entry_type_ff_14 (clk,rst_n,entry_type_wen_14 ,entry_type_nxt_14 ,entry_type_14 );
dffr #(.DW(5+1)) entry_id_ff_14   (clk,rst_n,entry_id_wen_14   ,entry_id_nxt_14   ,entry_id_14   );

dffr #(.DW(1)              ) entry_ready_ff_15(clk,rst_n,entry_ready_wen_15,entry_ready_nxt_15,entry_ready_15);
dffr #(.DW(1)              ) entry_type_ff_15 (clk,rst_n,entry_type_wen_15 ,entry_type_nxt_15 ,entry_type_15 );
dffr #(.DW(5+1)) entry_id_ff_15   (clk,rst_n,entry_id_wen_15   ,entry_id_nxt_15   ,entry_id_15   );

dffr #(.DW(1)              ) entry_ready_ff_16(clk,rst_n,entry_ready_wen_16,entry_ready_nxt_16,entry_ready_16);
dffr #(.DW(1)              ) entry_type_ff_16 (clk,rst_n,entry_type_wen_16 ,entry_type_nxt_16 ,entry_type_16 );
dffr #(.DW(5+1)) entry_id_ff_16   (clk,rst_n,entry_id_wen_16   ,entry_id_nxt_16   ,entry_id_16   );

dffr #(.DW(1)              ) entry_ready_ff_17(clk,rst_n,entry_ready_wen_17,entry_ready_nxt_17,entry_ready_17);
dffr #(.DW(1)              ) entry_type_ff_17 (clk,rst_n,entry_type_wen_17 ,entry_type_nxt_17 ,entry_type_17 );
dffr #(.DW(5+1)) entry_id_ff_17   (clk,rst_n,entry_id_wen_17   ,entry_id_nxt_17   ,entry_id_17   );

dffr #(.DW(1)              ) entry_ready_ff_18(clk,rst_n,entry_ready_wen_18,entry_ready_nxt_18,entry_ready_18);
dffr #(.DW(1)              ) entry_type_ff_18 (clk,rst_n,entry_type_wen_18 ,entry_type_nxt_18 ,entry_type_18 );
dffr #(.DW(5+1)) entry_id_ff_18   (clk,rst_n,entry_id_wen_18   ,entry_id_nxt_18   ,entry_id_18   );

dffr #(.DW(1)              ) entry_ready_ff_19(clk,rst_n,entry_ready_wen_19,entry_ready_nxt_19,entry_ready_19);
dffr #(.DW(1)              ) entry_type_ff_19 (clk,rst_n,entry_type_wen_19 ,entry_type_nxt_19 ,entry_type_19 );
dffr #(.DW(5+1)) entry_id_ff_19   (clk,rst_n,entry_id_wen_19   ,entry_id_nxt_19   ,entry_id_19   );

dffr #(.DW(1)              ) entry_ready_ff_20(clk,rst_n,entry_ready_wen_20,entry_ready_nxt_20,entry_ready_20);
dffr #(.DW(1)              ) entry_type_ff_20 (clk,rst_n,entry_type_wen_20 ,entry_type_nxt_20 ,entry_type_20 );
dffr #(.DW(5+1)) entry_id_ff_20   (clk,rst_n,entry_id_wen_20   ,entry_id_nxt_20   ,entry_id_20   );

dffr #(.DW(1)              ) entry_ready_ff_21(clk,rst_n,entry_ready_wen_21,entry_ready_nxt_21,entry_ready_21);
dffr #(.DW(1)              ) entry_type_ff_21 (clk,rst_n,entry_type_wen_21 ,entry_type_nxt_21 ,entry_type_21 );
dffr #(.DW(5+1)) entry_id_ff_21   (clk,rst_n,entry_id_wen_21   ,entry_id_nxt_21   ,entry_id_21   );

dffr #(.DW(1)              ) entry_ready_ff_22(clk,rst_n,entry_ready_wen_22,entry_ready_nxt_22,entry_ready_22);
dffr #(.DW(1)              ) entry_type_ff_22 (clk,rst_n,entry_type_wen_22 ,entry_type_nxt_22 ,entry_type_22 );
dffr #(.DW(5+1)) entry_id_ff_22   (clk,rst_n,entry_id_wen_22   ,entry_id_nxt_22   ,entry_id_22   );

dffr #(.DW(1)              ) entry_ready_ff_23(clk,rst_n,entry_ready_wen_23,entry_ready_nxt_23,entry_ready_23);
dffr #(.DW(1)              ) entry_type_ff_23 (clk,rst_n,entry_type_wen_23 ,entry_type_nxt_23 ,entry_type_23 );
dffr #(.DW(5+1)) entry_id_ff_23   (clk,rst_n,entry_id_wen_23   ,entry_id_nxt_23   ,entry_id_23   );

dffr #(.DW(1)              ) entry_ready_ff_24(clk,rst_n,entry_ready_wen_24,entry_ready_nxt_24,entry_ready_24);
dffr #(.DW(1)              ) entry_type_ff_24 (clk,rst_n,entry_type_wen_24 ,entry_type_nxt_24 ,entry_type_24 );
dffr #(.DW(5+1)) entry_id_ff_24   (clk,rst_n,entry_id_wen_24   ,entry_id_nxt_24   ,entry_id_24   );

dffr #(.DW(1)              ) entry_ready_ff_25(clk,rst_n,entry_ready_wen_25,entry_ready_nxt_25,entry_ready_25);
dffr #(.DW(1)              ) entry_type_ff_25 (clk,rst_n,entry_type_wen_25 ,entry_type_nxt_25 ,entry_type_25 );
dffr #(.DW(5+1)) entry_id_ff_25   (clk,rst_n,entry_id_wen_25   ,entry_id_nxt_25   ,entry_id_25   );

dffr #(.DW(1)              ) entry_ready_ff_26(clk,rst_n,entry_ready_wen_26,entry_ready_nxt_26,entry_ready_26);
dffr #(.DW(1)              ) entry_type_ff_26 (clk,rst_n,entry_type_wen_26 ,entry_type_nxt_26 ,entry_type_26 );
dffr #(.DW(5+1)) entry_id_ff_26   (clk,rst_n,entry_id_wen_26   ,entry_id_nxt_26   ,entry_id_26   );

dffr #(.DW(1)              ) entry_ready_ff_27(clk,rst_n,entry_ready_wen_27,entry_ready_nxt_27,entry_ready_27);
dffr #(.DW(1)              ) entry_type_ff_27 (clk,rst_n,entry_type_wen_27 ,entry_type_nxt_27 ,entry_type_27 );
dffr #(.DW(5+1)) entry_id_ff_27   (clk,rst_n,entry_id_wen_27   ,entry_id_nxt_27   ,entry_id_27   );

dffr #(.DW(1)              ) entry_ready_ff_28(clk,rst_n,entry_ready_wen_28,entry_ready_nxt_28,entry_ready_28);
dffr #(.DW(1)              ) entry_type_ff_28 (clk,rst_n,entry_type_wen_28 ,entry_type_nxt_28 ,entry_type_28 );
dffr #(.DW(5+1)) entry_id_ff_28   (clk,rst_n,entry_id_wen_28   ,entry_id_nxt_28   ,entry_id_28   );

dffr #(.DW(1)              ) entry_ready_ff_29(clk,rst_n,entry_ready_wen_29,entry_ready_nxt_29,entry_ready_29);
dffr #(.DW(1)              ) entry_type_ff_29 (clk,rst_n,entry_type_wen_29 ,entry_type_nxt_29 ,entry_type_29 );
dffr #(.DW(5+1)) entry_id_ff_29   (clk,rst_n,entry_id_wen_29   ,entry_id_nxt_29   ,entry_id_29   );

dffr #(.DW(1)              ) entry_ready_ff_30(clk,rst_n,entry_ready_wen_30,entry_ready_nxt_30,entry_ready_30);
dffr #(.DW(1)              ) entry_type_ff_30 (clk,rst_n,entry_type_wen_30 ,entry_type_nxt_30 ,entry_type_30 );
dffr #(.DW(5+1)) entry_id_ff_30   (clk,rst_n,entry_id_wen_30   ,entry_id_nxt_30   ,entry_id_30   );

dffr #(.DW(1)              ) entry_ready_ff_31(clk,rst_n,entry_ready_wen_31,entry_ready_nxt_31,entry_ready_31);
dffr #(.DW(1)              ) entry_type_ff_31 (clk,rst_n,entry_type_wen_31 ,entry_type_nxt_31 ,entry_type_31 );
dffr #(.DW(5+1)) entry_id_ff_31   (clk,rst_n,entry_id_wen_31   ,entry_id_nxt_31   ,entry_id_31   );



endmodule


